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    Towards minimizing the risks of soft errors at the design level of embedded systems

    Access Status
    Fulltext not available
    Authors
    Sadi, Muhammad Sheikh
    Date
    2009
    Supervisor
    Dr. Douglas Myers
    Type
    Thesis
    Award
    PhD
    
    Metadata
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    School
    Department of Electrical and Computer Engineering
    URI
    http://hdl.handle.net/20.500.11937/1300
    Collection
    • Curtin Theses
    Abstract

    The risks of soft errors increase with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. Research into techniques to cope with soft errors has mostly focused on post-design phases such as circuit level solutions, logic level solutions, spatial redundancy, temporal redundancy, and/or error correction codes. Clearly, though, it would be better to tackle the issue early in the design process. A novel method is outlined in this research for assigning a criticality ranking to the components in a design at the conceptual phase. The ranking is easily derived with little computational effort. Further, the research flags why the component is critical. The model is then examined by refactoring to lower each component’s criticality until the goal of minimising the risks of soft errors is satisfied and constraints are maintained. The methodology is then tested against real-life systems that must have high reliability.

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    • A Design Approach for Soft Errors Protection in Real-Time Systems
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      This paper proposes the use of metrics to refine system design for soft errors protection in system on chip architectures. Specifically this research shows the use of metrics in design space exploration that highlight ...
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