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    Design and synthesis of reversible arithmetic and Logic Unit (ALU)

    Access Status
    Fulltext not available
    Authors
    Gopal, Lenin
    Mohd Mahayadin, N.
    Chowdhury, A.
    Gopalai, A.
    Singh, A.
    Date
    2014
    Type
    Conference Paper
    
    Metadata
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    Citation
    Gopal, L. and Mohd Mahayadin, N. and Chowdhury, A. and Gopalai, A. and Singh, A. 2014. Design and synthesis of reversible arithmetic and Logic Unit (ALU), in International Conference on Computer, Communications, and Control Technology (I4CT), pp. 289-293: Institute of Electrical and Electronics Engineers Inc.
    Source Title
    I4CT 2014 - 1st International Conference on Computer, Communications, and Control Technology, Proceedings
    DOI
    10.1109/I4CT.2014.6914191
    ISBN
    9781479945559
    School
    Curtin Sarawak
    URI
    http://hdl.handle.net/20.500.11937/14507
    Collection
    • Curtin Research Publications
    Abstract

    In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

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