Boost Rectifier Power Factor Correction Circuits with Improved Harmonic and Load Voltage Regulation Responses
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The time domain step response for rapid load changes can be improved in boost type power factor correction circuits by using a capacitor voltage model. In single phase PFC circuits, the dc bus voltage must have a significant voltage ripple at twice the mains frequency due to energy balance requirements. In traditional implementations, the presence of this ripple voltage causes a trade-off between line current wave shape and speed of the dc output regulatory response. The capacitor voltage model provides a ripple free estimate of the storage capacitor voltage. This allows the bandwidth of the dc bus voltage regulation loop to increase without causing a degradation of line current wave shape. Simulations show that the dc regulatory response is complete within one mains cycle and significant reductions in voltage over and under-shoots are achieved.
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