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    Boost Rectifier Power Factor Correction Circuits with Improved Harmonic and Load Voltage Regulation Responses

    136211_136211.pdf (553.4Kb)
    Access Status
    Open access
    Authors
    Wolfs, Peter
    Thomas, P
    Date
    2007
    Type
    Conference Paper
    
    Metadata
    Show full item record
    Citation
    Wolfs, Peter and Thomas, P. 2007. Boost Rectifier Power Factor Correction Circuits with Improved Harmonic and Load Voltage Regulation Responses, in Unknown (ed), Power Electronics Specialists Conference, 2007. PESC 2007. IEEE, Jun 17 2007, pp. 1314-1318. Florida USA: IEEE.
    Source Title
    Power Electronics Specialists Conference
    Source Conference
    Power Electronics Specialists Conference, 2007. PESC 2007. IEEE
    ISBN
    1-4244-0655-2
    Faculty
    Department of Electrical and Computer Engineering
    School of Engineering
    Faculty of Science and Engineering
    Remarks

    Copyright © 2007 IEEE This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

    URI
    http://hdl.handle.net/20.500.11937/19531
    Collection
    • Curtin Research Publications
    Abstract

    The time domain step response for rapid load changes can be improved in boost type power factor correction circuits by using a capacitor voltage model. In single phase PFC circuits, the dc bus voltage must have a significant voltage ripple at twice the mains frequency due to energy balance requirements. In traditional implementations, the presence of this ripple voltage causes a trade-off between line current wave shape and speed of the dc output regulatory response. The capacitor voltage model provides a ripple free estimate of the storage capacitor voltage. This allows the bandwidth of the dc bus voltage regulation loop to increase without causing a degradation of line current wave shape. Simulations show that the dc regulatory response is complete within one mains cycle and significant reductions in voltage over and under-shoots are achieved.

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