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    Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-Variable Circuits

    154121_154121.pdf (498.1Kb)
    Access Status
    Open access
    Authors
    Prasad, P.
    Beg, A.
    Singh, Ashutosh Kumar
    Date
    2010
    Type
    Conference Paper
    
    Metadata
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    Citation
    Prasad, P.W.C. and Beg, Azam and Singh, Ashutosh Kumar. 2010. Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-Variable Circuits, 2nd International Conforence on Education Technology and Computer (ICETC), Jun 22 2010, pp. 134-138. Shanghai, China: IEEE.
    Source Title
    IEEE Proceeding
    Source Conference
    2nd International Conforence on Education Technology and Computer (ICETC)
    School
    Curtin Sarawak - Faculty Office
    Remarks

    Copyright © 2010 IEEE This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

    URI
    http://hdl.handle.net/20.500.11937/21256
    Collection
    • Curtin Research Publications
    Abstract

    In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.

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