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Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-Variable Circuits

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Date
2010
Type
Conference Paper

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Abstract

In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.

Citation
Prasad, P.W.C. and Beg, Azam and Singh, Ashutosh Kumar. 2010. Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-Variable Circuits, 2nd International Conforence on Education Technology and Computer (ICETC), Jun 22 2010, pp. 134-138. Shanghai, China: IEEE.
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IEEE Proceeding
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Curtin Sarawak - Faculty Office
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