High performance of RSA simulation system based on modified montgomery algorithm
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In order to eliminate the effect of the factor R-1 and decrease the number of iteration of modular exponentiation algorithm, a high performance scalable of Right-to-Left scan public-key cipher RSA simulation system is proposed. An advanced high radix Montgomery modular multiplication algorithm is presented to calculate by using an adder and a shift register, and the complexity of the circuit is minimized. The computation kernel of the device is two 32 bits multipliers with pipelining architecture, and it operates concurrently. The result of the hardware implementation shows that the improved RSA coprocessor is synthesized by CSMC 0.18um library, the area optimization design of 42 k gates with 213 ms/RSA are obtained to complete a 1024 bits encryption at 10 MHz. Compared with previous works, the proposed architecture can achieve better performance for the chip area and speed.