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Reconfigurable FIR Filter in FPGA

Access Status
Open access
Authors
Dzukleski, Igor
Ortega-Sanchez, Cesar
Date
2006
Type
Conference Paper

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Citation
Dzukleski, Igor and Ortega-Sanchez, Cesar. 2006. : Reconfigurable FIR Filter in FPGA, in ., Murdoch University (ed), Postgraduate Electrical Engineering and Computing Symposium, Nov 07 2006, pp. 149-152. Murdoch University, WA: Murdoch University.
Source Title
Procs. 7th Postgraduate Electrical Engineering and Computing Symposium
Source Conference
Postgraduate Electrical Engineering and Computing Symposium
Faculty
Faculty of Engineering and Computing
Department of Electrical and Computer Engineering
Division of Engineering, Science and Computing
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Abstract

Finite Impulse Response (FIR) filters are widely used in Digital Signal Processing (DSP) systems. The throughput of real-time, FIR filters is limited by the processing capability of its implementation. Software implementations are very flexible but the inherent sequential execution of programs makes them slow. The fastest FIR filters are those implemented in dedicated hardware, but these systems are usually fixed and modifications to the filter are not possible. This paper presents the design and implementation of a Field-Programmable Gate-Array (FPGA)-based, FIR filter. By exploiting the field-programmability of FPGAs it is possible to create different filters with fixed functionality, or even create adaptive filters whose parameters are adjusted in real-time by some intelligent algorithm.