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    Reconfigurable PDA for the Visually Impaired Using FPGAs

    135321_135321.pdf (240.4Kb)
    Access Status
    Open access
    Authors
    Zhang, Xuan
    Ortega-Sanchez, Cesar
    Murray, Iain
    Date
    2008
    Type
    Conference Paper
    
    Metadata
    Show full item record
    Citation
    Zhang, Xuan and Ortega-Sanchez, Cesar and Murray, Iain. 2008. Reconfigurable PDA for the Visually Impaired Using FPGAs, in Ceballos, S. (ed), International Conference on ReConFigurable Computing and FPGAs 2008, Dec 3 2008, pp. 1-6. Cancun, Mexico: IEEE.
    Source Title
    Proceedings of ReConFig?08
    Source Conference
    International Conference on ReConFigurable Computing and FPGAs 2008
    ISBN
    978-1-4244-3748-1
    Faculty
    Department of Electrical and Computer Engineering
    School of Engineering
    Faculty of Science and Engineering
    Remarks

    Copyright © 2009 IEEE This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

    URI
    http://hdl.handle.net/20.500.11937/5521
    Collection
    • Curtin Research Publications
    Abstract

    Curtin University Brailler (CUB) is a Personal Digital Assistant (PDA) for visually impaired people. Its objective is to make information in different formats accessible to people with limited visual ability. This paper presents the design and implementation of two modules: a print-to-Braille translation system and a Braille keyboard controller. The translator implements Blenkhorn's algorithm in hardware, liberating the microprocessor to perform other functions. The Braille keyboard controller along with a low cost keyboard provides users with a note-taking function. These modules are used as intellectual property (IP) cores coupled to a 32-bit MicroBlaze processor in an embedded system-on-a-chip (SoC). In its current implementation, the microprocessor uses a hierarchical interrupt scheme to coordinate IP cores. A prototype of the complete embedded system is under development using Xilinx's FPGAs. The system is a potential platform for the development of embedded systems to assist the visually impaired.

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