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    A Novel Generalized Concept for Three Phase Cascaded Multilevel Inverter Topologies

    254690.pdf (321.6Kb)
    Access Status
    Open access
    Authors
    Hasan, M.
    Abu-Siada, Ahmed
    Islam, S.
    Muyeen, S.M.
    Date
    2017
    Type
    Conference Paper
    
    Metadata
    Show full item record
    Citation
    Hasan, M. and Abu-Siada, A. and Islam, S. and Muyeen, S.M. 2017. A Novel Generalized Concept for Three Phase Cascaded Multilevel Inverter Topologies, in Proceedings of the 9th Annual IEEE Green Technologies Conference, Mar 29-31 2017, pp. 110-117. Denver, Colorado, USA: IEEE.
    Source Title
    IEEE Green Technologies Conference
    DOI
    10.1109/GreenTech.2017.22
    ISBN
    9781509045358
    School
    Department of Electrical and Computer Engineering
    Remarks

    © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

    URI
    http://hdl.handle.net/20.500.11937/55926
    Collection
    • Curtin Research Publications
    Abstract

    Many new cascaded multilevel inverter (MLI) topologies have recently been proposed and published in the literature. All proposed topologies demand significant amount of semiconductor components and input dc supplies, which is considered the main drawback for the implementation of three phase cascaded MLIs. This paper proposes a new generalized concept that could be employed within any existing cascaded MLI topology in order to reduce its size in terms of device count including semiconductor switches, diodes, and dc power supplies. The new generalized concept involves two stages namely, cascaded stage (CS) and phase generator stage (PGS). The PGS stage is a combination of conventional three phase two level inverter (CTPTLI) and three bidirectional (BD) switches, while the cascaded stage can be modified using any existing cascaded topology. The proposed concept is validated through extensive simulation and experimental analyses. Results show the capability of the proposed technique in reducing device count of the existing topologies while maintaining its performance.

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