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dc.contributor.authorYiu, Ka Fai
dc.contributor.authorLu, Y.
dc.contributor.authorHo, C.
dc.contributor.authorLuk, W.
dc.contributor.authorHuo, Jiaquan
dc.contributor.authorNordholm, Sven
dc.date.accessioned2017-01-30T10:54:33Z
dc.date.available2017-01-30T10:54:33Z
dc.date.created2015-03-03T20:17:20Z
dc.date.issued2012
dc.identifier.citationYiu, K.F. and Lu, Y. and Ho, C. and Luk, W. and Huo, J. and Nordholm, S. 2012. Reconfigerable FPGA-based switching path frequency-domain echo canceller with applications to voice control device. Digital Signal Processing. 22 (2): pp. 376-390.
dc.identifier.urihttp://hdl.handle.net/20.500.11937/6665
dc.identifier.doi10.1016/j.dsp.2011.10.008
dc.description.abstract

Acoustic echo control is of vital interest for hands-free operation of telecommunications equipment. An important property of an acoustic echo canceller is its capability to handle double-talk and be able to operate in real time. When it is applied to intelligent voice control device, it is important to suppress the speech from the device and enhance the speech of the user for speech recognition, where double-talk situation is frequently occurred. In this paper, we propose a novel hardware architecture to support a robust adaptive algorithm in combination with a switching path model to tackle the double-talk situation. The proposed switching path model avoids adapting two filters at the same time during double-talk and prevents the disadvantage of the conventional two-path model. In order to achieve computational efficiency and to meet the rigorous timing requirements, the echo canceller is operated in the frequency domain and its computing power is raised by a hardware accelerator implemented in the FPGA fabric surrounding a PowerPC on a Xilinx XUP V2P platform. Results obtained show the echo canceller is successful in handling double-talk situation and the sub-band implementation has improved convergence significantly. An overall improvement by 82.5 times is achieved when a hardware accelerator is used to perform the critical part of the algorithm over a pure software implementation running on a 300 MHz embedded PowerPC processor.

dc.publisherAcademic Press
dc.titleReconfigerable FPGA-based switching path frequency-domain echo canceller with applications to voice control device
dc.typeJournal Article
dcterms.source.volume22
dcterms.source.number2
dcterms.source.startPage376
dcterms.source.endPage390
dcterms.source.issn10512004
dcterms.source.titleDigital Signal Processing
curtin.accessStatusFulltext not available


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