View Item 

FPGA implementation of wideband IQ imbalance correction in OFDM receivers

Access Status
Open access
Authors
Palipana, Rajitha
Chung, Kah-Seng
Date
2008
Type
Conference Paper

Metadata
Show full item record
Citation
Palipana, Rajitha and Chung, Kah-Seng. 2008. FPGA implementation of wideband IQ imbalance correction in OFDM receivers, in ICCSC 2008 Technical Program Committee (ed), 4th IEEE International Conference on Circuits and Systems for Communications. ICCSC 2008, May 26 2008, pp. 663-667, Shanghai, China: IEEE eXpress Conference Publishing.
Source Title
Proceedings of IEEE International Conference on Circuits and Systems for Communications
Source Conference
4th IEEE International Conference on Circuits and Systems for Communications ICCSC 2008
DOI
ISBN
Faculty
School of Electrical Engineering and Computing
Department of Electrical and Computer Engineering
Science and Engineering
Remarks

Copyright © 2008 IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

URI
Collection
Abstract

This paper describes the implementation of a digital compensation scheme, called CSAD, for correcting the effects of wideband gain and phase imbalances in dual-branch OFDM receivers. The proposed scheme is implemented on a Xilinx Virtex-4 field programmable gate array (FPGA). The flexible architecture of the implementation makes it readily adaptable for different broadband applications, such as DVB-T/H, WLAN, and WiMAX. The proposed correction scheme is resilient against multipath fading and frequency offset. When applied to DVB-T, it is shown that an 11-bit arithmetic precision is sufficient to achieve the required BER of 2x10-4 at an SNR of 16.5 dB. Using this bit-precision, the implementation consumes 1686 Virtex-4 slices equivalent to about 42600 gates.