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FPGA implementation of wideband IQ imbalance correction in OFDM receivers

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2008
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Conference Paper

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Abstract

This paper describes the implementation of a digital compensation scheme, called CSAD, for correcting the effects of wideband gain and phase imbalances in dual-branch OFDM receivers. The proposed scheme is implemented on a Xilinx Virtex-4 field programmable gate array (FPGA). The flexible architecture of the implementation makes it readily adaptable for different broadband applications, such as DVB-T/H, WLAN, and WiMAX. The proposed correction scheme is resilient against multipath fading and frequency offset. When applied to DVB-T, it is shown that an 11-bit arithmetic precision is sufficient to achieve the required BER of 2x10-4 at an SNR of 16.5 dB. Using this bit-precision, the implementation consumes 1686 Virtex-4 slices equivalent to about 42600 gates.

Citation
Palipana, Rajitha and Chung, Kah-Seng. 2008. FPGA implementation of wideband IQ imbalance correction in OFDM receivers, in ICCSC 2008 Technical Program Committee (ed), 4th IEEE International Conference on Circuits and Systems for Communications. ICCSC 2008, May 26 2008, pp. 663-667, Shanghai, China: IEEE eXpress Conference Publishing.
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Proceedings of IEEE International Conference on Circuits and Systems for Communications
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School of Electrical Engineering and Computing
Department of Electrical and Computer Engineering
Science and Engineering
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