Design of reversible multiplexer/de-multiplexer
|dc.identifier.citation||Gopal, L. and Raj, N. and Gopalai, A. and Singh, A. 2014. Design of reversible multiplexer/de-multiplexer, in 2014 IEEE International Conference on Control System, Computing and Engineering (ICCSCE), pp. 416-420. Batu Ferringhi: Institute of Electrical and Electronics Engineers Inc.|
© 2014 IEEE. Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic logical functions such as AND, XOR, MUX etc. Besides these functions, other advantage of the proposed R-I gate is that it can be used as a 1/2 de-multiplexer without requiring any extra logic circuits and the proposed R-II gate can be used as a half adder circuit. The proposed reversible gates are implemented and verified using Xilinx ISE 10.1 software. The simulation results show that the proposed designs are more efficient in terms of gate count, garbage outputs and constant inputs than the existing reversible logic gate.
|dc.publisher||Institute of Electrical and Electronics Engineers Inc.|
|dc.title||Design of reversible multiplexer/de-multiplexer|
|dcterms.source.title||Proceedings - 4th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2014|
|dcterms.source.series||Proceedings - 4th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2014|
|curtin.accessStatus||Fulltext not available|
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