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    Steady-State Analysis and Designing Impedance Network of Z-Source Inverters

    160617_30533_STeady-State Analysis and Designing.pdf (363.3Kb)
    Access Status
    Open access
    Authors
    Rajakaruna, Sumedha
    Jayawickrama, L
    Date
    2010
    Type
    Journal Article
    
    Metadata
    Show full item record
    Citation
    Rajakaruna, S. and Jayawickrama, L. 2010. Steady-State Analysis and Designing Impedance Network of Z-Source Inverters. IEEE Transactions on Industrial Electronics 57 (7): pp. 2483-2491.
    Source Title
    IEEE Transactions on Industrial Electronics
    DOI
    10.1109/TIE.2010.2047990
    ISSN
    02780046
    School
    Department of Electrical and Computer Engineering
    Remarks

    Copyright © 2010 IEEE This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

    URI
    http://hdl.handle.net/20.500.11937/29546
    Collection
    • Curtin Research Publications
    Abstract

    All possible steady states of a Z-source inverter are identified and analyzed with the objective of deriving design guidelines for the symmetrical impedance network. This paper shows that, in addition to the desired three dynamic states, an operating cycle can contain another three static states that do not contribute to the power conversion process. These three static states can be avoided by selecting suitably large capacitors and inductors. By using the equations derived in the steady-state analysis, this paper presents guidelines to design the impedance network accurately for the case where the inverter is operated only in active and shoot-through states. The proposed design method can also be used to predict the critical values of capacitance and inductance below which static states appear during the operating cycle. Computer simulations and laboratory experiments are used to verify the design method and to demonstrate the appearance of static states when the capacitors and inductors are sized lower than their critical values.

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