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dc.contributor.authorRajakaruna, Sumedha
dc.contributor.authorJayawickrama, L
dc.identifier.citationRajakaruna, S. and Jayawickrama, L. 2010. Steady-State Analysis and Designing Impedance Network of Z-Source Inverters. IEEE Transactions on Industrial Electronics 57 (7): pp. 2483-2491.

All possible steady states of a Z-source inverter are identified and analyzed with the objective of deriving design guidelines for the symmetrical impedance network. This paper shows that, in addition to the desired three dynamic states, an operating cycle can contain another three static states that do not contribute to the power conversion process. These three static states can be avoided by selecting suitably large capacitors and inductors. By using the equations derived in the steady-state analysis, this paper presents guidelines to design the impedance network accurately for the case where the inverter is operated only in active and shoot-through states. The proposed design method can also be used to predict the critical values of capacitance and inductance below which static states appear during the operating cycle. Computer simulations and laboratory experiments are used to verify the design method and to demonstrate the appearance of static states when the capacitors and inductors are sized lower than their critical values.

dc.publisherInstitute of Electrical and Electronic Engineers
dc.titleSteady-State Analysis and Designing Impedance Network of Z-Source Inverters
dc.typeJournal Article
dcterms.source.titleIEEE Transactions on Industrial Electronics

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curtin.departmentDepartment of Electrical and Computer Engineering
curtin.accessStatusOpen access

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