Text-to-Braille Translator in a Chip
Access Status
Open access
Authors
Zhang, Xuan
Ortega-Sanchez, Cesar
Date
2006Type
Conference Paper
Metadata
Show full item recordCitation
Zhang, Xuan and Ortega-Sanchez, Cesar and Murray, Iain. 2006. Text-to-braille translator in a chip, in Proceedings of the 7th Postgraduate Electrical Engineering and Computing Symposium (PEECS 2006), Nov 07 2006, pp. 87-90. Perth, WA: Murdoch University.
Source Title
Proceedings of the 7th Postgraduate Electrical Engineering and Computing Symposium
Source Conference
Postgraduate Electrical Engineering and Computing Symposium
Faculty
Faculty of Engineering and Computing
Department of Electrical and Computer Engineering
Division of Engineering, Science and Computing
Collection
Abstract
This paper describes the hardware implementation of a text to Braille Translator using Field-Programmable Gate Arrays (FPGAs). Different from most commercial software-based translators, the circuit presented in this paper is able to carry out text-to-Braille translation in hardware. The translator is based on the translating algorithm, proposed by Paul Blenkhorn [1]. The Very high speed Hardware Description Language (VHDL) was used to describe the chip in a hierarchical way. The test results indicate that the hardware-based translator achieves the same results as software-based commercial translators, with superior throughput.
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