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dc.contributor.authorZhang, Xuan
dc.contributor.authorOrtega-Sanchez, Cesar
dc.identifier.citationZhang, Xuan and Ortega-Sanchez, Cesar and Murray, Iain. 2006. Text-to-braille translator in a chip, in Proceedings of the 7th Postgraduate Electrical Engineering and Computing Symposium (PEECS 2006), Nov 07 2006, pp. 87-90. Perth, WA: Murdoch University.

This paper describes the hardware implementation of a text to Braille Translator using Field-Programmable Gate Arrays (FPGAs). Different from most commercial software-based translators, the circuit presented in this paper is able to carry out text-to-Braille translation in hardware. The translator is based on the translating algorithm, proposed by Paul Blenkhorn [1]. The Very high speed Hardware Description Language (VHDL) was used to describe the chip in a hierarchical way. The test results indicate that the hardware-based translator achieves the same results as software-based commercial translators, with superior throughput.

dc.publisherMurdoch University
dc.subjectAssistive Technology
dc.subjectembedded systems
dc.subjectBraille Translation
dc.titleText-to-Braille Translator in a Chip
dc.typeConference Paper
dcterms.source.titleProceedings of the 7th Postgraduate Electrical Engineering and Computing Symposium
dcterms.source.seriesProcs. 7th Postgraduate Electrical Engineering and Computing Symposium
dcterms.source.conferencePostgraduate Electrical Engineering and Computing Symposium
dcterms.source.conference-start-dateNov 07 2006
dcterms.source.conferencelocationMurdoch University, WA
dcterms.source.placePerth, WA
curtin.accessStatusOpen access
curtin.facultyFaculty of Engineering and Computing
curtin.facultyDepartment of Electrical and Computer Engineering
curtin.facultyDivision of Engineering, Science and Computing

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