Efficient methods for synthesis of multivalued logic
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Multi-Valued Logic (MVL) synthesis has economically revolutionized the method of designing logic functions. MVL has become an alternative to our universal binary logic. In this thesis, as a branch of emerging technology, MVL is considered for circuit simplification and size reduction. Reduced MVL circuits are obtained by efficient synthesis algorithms. Different approaches on synthesizing techniques are investigated. Synthesized circuits are demonstrated with dynamic and static performances over binary and existing MVL techniques.
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