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    Efficient methods for synthesis of multivalued logic

    226049_Chowdhury, Adib Kabir 2015.pdf (2.368Mb)
    Access Status
    Open access
    Authors
    Chowdhury, Adib Kabir
    Date
    2014
    Supervisor
    Prof. Ashutosh Kumar Singh
    Mr. Lenin Gopal
    Type
    Thesis
    Award
    MPhil
    
    Metadata
    Show full item record
    School
    School of Electrical and Computing
    URI
    http://hdl.handle.net/20.500.11937/335
    Collection
    • Curtin Theses
    Abstract

    Multi-Valued Logic (MVL) synthesis has economically revolutionized the method of designing logic functions. MVL has become an alternative to our universal binary logic. In this thesis, as a branch of emerging technology, MVL is considered for circuit simplification and size reduction. Reduced MVL circuits are obtained by efficient synthesis algorithms. Different approaches on synthesizing techniques are investigated. Synthesized circuits are demonstrated with dynamic and static performances over binary and existing MVL techniques.

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