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dc.contributor.authorChowdhury, Adib Kabir
dc.contributor.supervisorProf. Ashutosh Kumar Singh
dc.contributor.supervisorMr. Lenin Gopal
dc.date.accessioned2017-01-30T09:48:54Z
dc.date.available2017-01-30T09:48:54Z
dc.date.created2015-05-14T06:55:53Z
dc.date.issued2014
dc.identifier.urihttp://hdl.handle.net/20.500.11937/335
dc.description.abstract

Multi-Valued Logic (MVL) synthesis has economically revolutionized the method of designing logic functions. MVL has become an alternative to our universal binary logic. In this thesis, as a branch of emerging technology, MVL is considered for circuit simplification and size reduction. Reduced MVL circuits are obtained by efficient synthesis algorithms. Different approaches on synthesizing techniques are investigated. Synthesized circuits are demonstrated with dynamic and static performances over binary and existing MVL techniques.

dc.languageen
dc.publisherCurtin University
dc.titleEfficient methods for synthesis of multivalued logic
dc.typeThesis
dcterms.educationLevelMPhil
curtin.departmentSchool of Electrical and Computing
curtin.accessStatusOpen access


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