A system for fast Text-to-Braille translation based on FPGAs

Zhang, Xuan; Ortega-Sanchez, Cesar; Murray, Iain

doi:10.1109/SPL.2007.371735

117495_A%20system%20for%20fast%20PID%20117495.pdf (5.082Mb)

Access Status

Open access

Authors

Zhang, Xuan

Ortega-Sanchez, Cesar

Murray, Iain

Date

2007

Type

Conference Paper

Metadata

Show full item record

Citation

Zhang, Xuan and Ortega-Sanchez, Cesar and Murray, Iain. 2007. A system for fast Text-to-Braille translation based on FPGAs, in Boemo, E. et. al. (ed), 3rd Southern Conference on Programmable Logic (SPL '07), Feb 26 2007, pp. 125-130. Mar del Plata, Argentina: Institute of Electrical and Electronics Engineers (IEEE).

Source Title

Proceedings of the 2007 3rd Southern Conference on Programmable Logic

Source Conference

3rd Southern Conference on Programmable Logic

DOI

10.1109/SPL.2007.371735

ISBN

1424406064

Faculty

School of Electrical Engineering and Computing

Department of Electrical and Computer Engineering

Faculty of Science and Engineering

Remarks

Copyright © 2007 IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

URI

http://hdl.handle.net/20.500.11937/36235

Collection

Curtin Research Publications

Abstract

This paper describes a fast text to Braille translator based on Field Programmable Gate Arrays (FPGAs). Compared with most commercial methods, this translator is able to carry out the translation in hardware instead of using software. To achieve the fast translation, a FPGA with big programmable resource has been utilized, and an algorithm, proposed by Paul Blenkhorn, has been revised to perform the fast translation. The translator has been described using Very high speed integrated circuit Hardware Description Language (VHDL). The test results indicate that the hardware-based translator achieves the same results as software-based commercial translators, and moreover, this system achieves superior throughput compared to Blenkhorn's original algorithm.