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    PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems

    Access Status
    Fulltext not available
    Authors
    Dargahi, M.
    Ghosh, Arindam
    Ledwich, G.
    zare, F.
    Date
    2012
    Type
    Conference Paper
    
    Metadata
    Show full item record
    Citation
    Dargahi, M. and Ghosh, A. and Ledwich, G. and zare, F. 2012. PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems, in Dr Tomy Sebastian, Nexteer Automotive Future Enginering (ed), PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems, Dec 16 2012. Bengaluru, Karnataka; India: Institute of Electrical and Electronics Engineers ( IEEE ).
    Source Title
    Studies in power hardware in the loop (PHIL) simulation using real-time digital simulator (RTDS)
    Source Conference
    PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems
    ISBN
    978-1-4673-4508-8
    URI
    http://hdl.handle.net/20.500.11937/8914
    Collection
    • Curtin Research Publications
    Abstract

    In power hardware in the loop (PHIL) simulations, a real-time simulated power system is interfaced to a piece of hardware, usually called hardware under test (HuT). A PHIL test can be realized using several simulation tools. Among them Real Time Digital Simulator (RTDS) is an ideal tool to perform complex power system simulations in near real-time. Stable operation of the entire system, along with the accuracy of simulation results are the main concerns regarding a PHIL simulation. In this paper, a simulated power network on RTDS will be interfaced to HuT through a voltage source converter (VSC). Issues around stability and other interface problems are studied and a new method to stabilize some unstable PHIL cases is proposed. PHIL simulation results in PSCAD and RSCAD are presented.

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