Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
MetadataShow full item record
An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 m CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base.
Showing items related by title, author, creator and subject.
Singh, Ashutosh Kumar; Bera, A.; Rahaman, H.; Mathew, J.; Pradhan, D.k. (2009)This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation ...
Hodgson, J.; Zhu, K.; Lewis, J.; Kerr, Deborah; Meng, Xingqiong; Solah, Vicky; Devine, A.; Binns, Colin; Woodman, J.; Prince, R. (2012)Short-term randomised, controlled trials have found that dietary protein relative to carbohydrate can reduce blood pressure. Our objective was to investigate the effects on blood pressure of an increase in protein intake ...
Elastin fibers display a versatile microfibril network in articular cartilage depending on the mechanical microenvironmentsHe, Bo; Wu, Jianping; Chen, Honghui; Kirk, Thomas; Xu, Jiake (2013)Elastin fibers are major extracellular matrix macromolecules that are critical in maintaining the elasticity and resilience of tissues such as blood vessels, lungs and skins. However, the role of elastin in articular ...