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    Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

    134012_16545_10-DCS-03_336-342_.pdf (597.2Kb)
    Access Status
    Open access
    Authors
    Singh, Ashutosh Kumar
    Bera, A.
    Rahaman, H.
    Mathew, J.
    Pradhan, D.
    Date
    2009
    Type
    Journal Article
    
    Metadata
    Show full item record
    Citation
    Singh, A. and Bera, A. and Rahaman, H. and Mathew, J. and Pradhan, D. 2009. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m). Journal of Electronic Science and Technology. 7 (4): pp. 336-342.
    Source Title
    Journal of Electronic Science and Technology of China
    ISSN
    16726464
    Faculty
    Sarawak
    Department of Electrical & Computer Engineering
    School of Engineering and Science
    Miri Campus
    School
    Curtin Sarawak - Faculty Office
    URI
    http://hdl.handle.net/20.500.11937/20443
    Collection
    • Curtin Research Publications
    Abstract

    An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 m CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base.

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