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dc.contributor.authorSingh, Ashutosh Kumar
dc.contributor.authorBera, A.
dc.contributor.authorRahaman, H.
dc.contributor.authorMathew, J.
dc.contributor.authorPradhan, D.
dc.identifier.citationSingh, A. and Bera, A. and Rahaman, H. and Mathew, J. and Pradhan, D. 2009. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m). Journal of Electronic Science and Technology. 7 (4): pp. 336-342.

An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 m CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base.

dc.publisherUniversity of Electronic Science and Technology
dc.subjectReed-Solomon (RS) codes
dc.subjecterror correction
dc.subjectfinite field
dc.subjectBit parallel
dc.subjectvery large scale integration (VLSI) testing
dc.titleError Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
dc.typeJournal Article
dcterms.source.titleJournal of Electronic Science and Technology of China
curtin.departmentCurtin Sarawak - Faculty Office
curtin.accessStatusOpen access
curtin.facultyDepartment of Electrical & Computer Engineering
curtin.facultySchool of Engineering and Science
curtin.facultyMiri Campus

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