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Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

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Open access
Authors
Singh, Ashutosh Kumar
Bera, A.
Rahaman, H.
Mathew, J.
Pradhan, D.k.
Date
2009
Type
Conference Paper

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Citation
Singh, A. and Bera, A. and Rahaman, H. and Mathew, J. and Pradhan, D. 2009. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m), in Long, B. (ed), IEEE Circuits and Systems International Conference on Testing and Diagnosis, Apr 28 2009, pp. 1-4. Chengdu, China: IEEE.
Source Title
IEEE Proceeding
Source Conference
IEEE Circuits and Systems International Conference on Testing and Diagnosis
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Faculty
Department of Electrical and Computer Engineering
School of Engineering
Faculty of Science and Engineering
School
Curtin Sarawak - Faculty Office
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Abstract

This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flow. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35um CMOS technology. This architecture can also operate over both the dual-base and polynomial base.