Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
| dc.contributor.author | Singh, Ashutosh Kumar | |
| dc.contributor.author | Bera, A. | |
| dc.contributor.author | Rahaman, H. | |
| dc.contributor.author | Mathew, J. | |
| dc.contributor.author | Pradhan, D.k. | |
| dc.contributor.editor | Long, Bing. | |
| dc.date.accessioned | 2017-01-30T13:24:25Z | |
| dc.date.available | 2017-01-30T13:24:25Z | |
| dc.date.created | 2010-03-14T20:02:21Z | |
| dc.date.issued | 2009 | |
| dc.identifier.citation | Singh, A. and Bera, A. and Rahaman, H. and Mathew, J. and Pradhan, D. 2009. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m), in Long, B. (ed), IEEE Circuits and Systems International Conference on Testing and Diagnosis, Apr 28 2009, pp. 1-4. Chengdu, China: IEEE. | |
| dc.identifier.uri | http://hdl.handle.net/20.500.11937/31256 | |
| dc.description.abstract |
This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flow. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35um CMOS technology. This architecture can also operate over both the dual-base and polynomial base. | |
| dc.publisher | IEEE Proceeding | |
| dc.subject | error correction | |
| dc.subject | Finite Field | |
| dc.subject | systolic | |
| dc.subject | VLSI Testing | |
| dc.subject | RS codes | |
| dc.subject | bit parallel | |
| dc.title | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) | |
| dc.type | Conference Paper | |
| dcterms.source.startPage | 1 | |
| dcterms.source.endPage | 4 | |
| dcterms.source.title | IEEE Proceeding | |
| dcterms.source.series | IEEE Proceeding | |
| dcterms.source.isbn | 9781424425877 | |
| dcterms.source.conference | IEEE Circuits and Systems International Conference on Testing and Diagnosis | |
| dcterms.source.conference-start-date | Apr 28 2009 | |
| dcterms.source.conferencelocation | Chengdu, China | |
| dcterms.source.place | China | |
| curtin.note |
Copyright © 2009 IEEE This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | |
| curtin.department | Curtin Sarawak - Faculty Office | |
| curtin.accessStatus | Open access | |
| curtin.faculty | Department of Electrical and Computer Engineering | |
| curtin.faculty | School of Engineering | |
| curtin.faculty | Faculty of Science and Engineering |