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dc.contributor.authorTing, K.P.
dc.contributor.authorSujan, Debnath
dc.contributor.editorF. E. Tang, ME Rahman, M V Prasana, L NGU, G. Rajamohan, Z Oo
dc.date.accessioned2017-01-30T13:25:00Z
dc.date.available2017-01-30T13:25:00Z
dc.date.created2013-03-18T20:00:54Z
dc.date.issued2012
dc.identifier.citationTing, K.P. and Sujan, D. 2012. Electronic Packaging Model with Continuous and Discontinuous Bond Layer, in Tang, F.E. et al. (ed), 7th Curtin University Conference (CUTSE): Engineering Goes Green, Nov 6-7 2012, pp. 357-362. Sarawak, Malaysia: Curtin University School of Engineering.
dc.identifier.urihttp://hdl.handle.net/20.500.11937/31369
dc.description.abstract

Interfacial stress due to thermal mismatch in layered structure has been considered as one of the major causes of mechanical failure in electronic packaging. The mismatch of the coefficient thermal expansion (CTE) of the materials in multiplayer structure may induce serious stress concentrations to the electronic composites such as interfacial delamitation and die cracking. Therefore, the studies and evaluation of interfacial stress in electronic packaging become significantly important for failure prediction optimum and design of the electronic devices. The thermal mismatch shear stress for hi-layered assembly can be analyzed by using the mathematical models developed by Suhir in 1986. In this research, Finite Element Method (FEM) simulation was performed to a packaging example by using ANSYS. The FEM results were compared to the analytical solutions to determine the validity of the results. The interfacial stresses were further studied with the consideration of continuous and discontinuous bonding in the assembly by analyzing the shear stress growth behavior at the interface of the bonded section. In addition, comparison of shear stress was made between continuous and discontinuous bonded hi-layered assemblies to evaluate their relative effect in electronic packaging. Furthermore, the interfacial stress analysis was carried out on discontinuously bonded Flip Chip Ball Grid Array (FCBGA) which is widely used in current electronic packaging industry. The interfacial stress distribution of FCBGA was analyzed.

dc.publisherSchool of Engineering & Science, Curtin University Sarawak Campus
dc.subjectBond layer
dc.subjectBi-layered assembly
dc.subjectThermal mismatch
dc.subjectFlip Chip Ball Grid Array
dc.subjectInterfacial shear stress
dc.titleElectronic Packaging Model with Continuous and Discontinuous Bond Layer
dc.typeConference Paper
dcterms.source.startPage357
dcterms.source.endPage362
dcterms.source.titleProceedings of the 7th Curtin University Conference (CUTSE) Engineering Goes Green
dcterms.source.seriesProceedings of the 7th Curtin University Conference (CUTSE) Engineering Goes Green
dcterms.source.isbn978-983-44482-3-3
dcterms.source.conference7th Curtin University Conference (CUTSE) Engineering Goes Green
dcterms.source.conference-start-dateNov 6 2012
dcterms.source.conferencelocationCurtin Sarawak, Malaysia
dcterms.source.placeMiri, Sarawak
curtin.department
curtin.accessStatusFulltext not available


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